Clifton Laboratories 7236 Clifton Road  Clifton VA 20124 tel: (703) 830 0368 fax: (703) 830 0711

E-mail: Jack.Smith@cliftonlaboratories.com
 

JFETs are notorious for having wide parameter spreads. It's not uncommon to see a 3:1 or even 5:1 ratio between the maximum and minimum parameter values.  I've spent the day measuring a collection of JFETs to see how much variation in transfer characteristics might be found.

Revision History
Written 16 December 2008

I_DSS—the drain current with zero gate voltage (gate at same voltage potential as source)

I_D versus V_GS Transfer Curve—how the drain current varies as the gate voltage changes, for a constant drain-to-source voltage.

The transfer curve is particularly useful in establishing component values for static bias conditions and estimating gain.

I looked at three device types I had on hand in my parts box:

• J310 N-channel FET
• J305 N-channel FET
• J271 P-channel FET

The J310 part I had in both TO-92 through-hole and SOT-23 surface mount packages, the J305 in TO-92 and the J271 in SOT-23.

The test setup I used is illustrated below. It uses a programmable DC multiple output power supply, an Agilent E3631A, to supply a constant drain-to-source voltage across the FET being tested and also to vary the gate-to-source voltage. The gate-to-source voltage is measured by an Agilent 34410A multi-meter, and the drain current is measured by an Agilent 34401A multi-meter.

The setup is controlled over the instruments' GPIB bus, using a Prologix USB-GPIB adapter and software I've written running under the EZGPIB instrument control framework. I've written  about the Prologix adapter and EZGPIB at EZGPIB and Prologix GPIB Adapter.

My approach has one important drawback, compared with how parameter measurements should be made. In order to avoid  thermal effects from altering the parameter being made, either a pulse or fast ramp signal is applied to the gate, which keeps the average power down, thereby reducing junction heating. By applying steady DC to the device being tested, particularly at higher current levels, the junction will heat, which causes parameters to shift from their normal room  temperature values. The data is taken with V_DS = 10V, which means that at 40 mA drain current, the device is dissipating 400 mW, an appreciable power for parts rated at a few hundred mW maximum.

There are two ways of looking at this. First, as said above, my measurements will not necessarily track the data sheet closely at high currents. Second, in many applications, the device is run at steady current, in which case my measurements may be more reflective of the real world than pulse measurements. Still, it's better to use data without thermal issues and apply the necessary temperature adjustment than to mix both parametric and thermal data.

I looked at I_DSS for 26 individual J310 N-channel FETs, in TO-92 (through hole) packages. I_DSS is the current flow through the device under test with zero gate current and thus represents the FET's maximum current under normal operating conditions, where the gate is reverse biased. With a N-channel FET, the gate is negative with respect to the source. When designing with a single polarity (positive to ground) supply, the N-channel's bias is often obtained by adding a resistor from the source to ground, which elevates the source above ground. If the gate is then tied back to ground with a high value resistor, the gate-to-source voltage is thus negative.

The figure below shows the distribution of I_DSS values amongst the 26 devices.

The 26 devices consisted of 22 manufactured by ON SEMI, all with the same date code, 2 manufactured by Motorola, with the same date code and 2 manufactured by Fairchild, with the same date code. (ON SEMI is the successor to Motorola's RF semiconductor business.) I should have, but did not, note which devices were from each manufacturer.

Not surprisingly, as I_DSS is an important parameter, all three manufacturers quote the same values. And, as my measurements show, all 26 devices are within this rather large range. Even my small sample, however, shows nearly a 2:1 range in I_DSS values.

The transfer curve below is from Philips Semiconductor's J310 data sheet (now NXP Semiconductor).

At 10 mA, NXP's curve calls for -1.6V gate bias, and the blue curve I measured is around -2.3V. At 5 mA, NXP's datasheet shows -2.0V bias while I measured -2.7V. At 20 mA, NXP's data shows -0.9V, and I measured -1.4V.

All in all, not all that close to the data sheet. However, looking at the data spread, some individual parts track NXP's datasheet values reasonably well.

Motorola's version of the transfer plot is provided below. The plot also shows another parameter, so concentrate on the curves labeled with the three temperature values. The three curves associated with +25°C, 50mA for 0 VGS is the correct curve family. (The three lower curves are for the J309, as the data sheet covers both devices.)

Note the differences. At 0V_GS and +25°C, Motorola's data shows 50 mA (this is I_DSS, of course) whilst NXP's data sheet shows 36 mA for the same condition. For 20 mA, Motorola shows -1.8V gate bias, and at 10 mA, -2.5V.

How do these all compare with my measured data?

With a wider view of manufacturer's data, my small sample of 26 parts fits within the expected range, with my measured means falling between Motorola and Fairchild's values. NXP seems to be the odd man out in this regard.

Many JFETs are said to be "symmetrical" which means that the source and drain leads may be interchanged without changing the device's performance. In theory, different schematic symbols should be used to distinguish a symmetrical FET from a non-symmetrical FET. This differentiation seems to be rarely used, however.
 

Incidentally, the kink in the transfer curve near 0V / 35 mA is almost certainly due to junction heating. At 10V and 35 mA, the device is dissipating 350 mW. In the SOT-23 surface mount package the maximum power rating is 225 mA, so it's no wonder that the junction has heated enough to show the effects of elevated temperature.

I don't have sufficient number of samples to definitively answer that question, but it seems the answer may be yes.

In my collection of J305 N-channel FETs, I found three plant//date codes. (These are Siliconix parts, I believe.) The plot below shows the transfer characteristics, Note that one pair of parts are so closely matched the line just appears to be thicker than normal, and a second pair (also the C224AA date code) are nearly as well matched, although differing from the first pair.